1. Field of the Invention
The invention relates to semiconductor technology and in particular to devices, for low gate voltage and higher drain breakdown performance.
2. Description of the Related Art
A complete circuit, such as an integrated circuit (IC), usually comprises thousands of transistors. A shallow trench isolation (STI) serves as an isolation region to prevent short circuit between two adjacent transistors. Such STI is formed by producing a shallow trench in a semiconductor substrate by anisotropically etching the semiconductor substrate using a silicon nitride layer as a hard mask, and then filling the shallow trench with an insulating layer.
The characteristics of STIs depend on whether the STI has a liner layer. However, defects, such as shallow pitting, may occur in an STI with no liner layer, due to subsequent oxidation. The defect degrades the electrical characteristics of the resultant device, and causes leakage current in a junction region, i.e., adversely affects the isolation of the device. In addition, since the shallow trench formed in the substrate is angulated at its top corner, a gate oxide layer grows insufficiently or non-uniformly during subsequent thermal oxidation. Hence, the portion of the gate oxide layer formed on the top corner of the shallow trench is very thin. As a result, breakdown voltage of the gate oxide layer on the active region becomes lower, and a parasitic current occurs in a transistor, thereby degrading the operability of the resultant device.
A semiconductor device is disclosed to improve the thickness distribution of the gate oxide proximate to the STI to improve breakdown voltage performance. The device comprises a step shallow trench structure. This structure effectively works in uniform gate oxide thickness but the gate oxide thickness is still thinner than other parts thereof. Thus, more effective structures and processes for improvement of the breakdown voltages are needed.